Scaling of features in integrated circuits enables increased densities of electronic devices on the limited real estate of the integrated circuit chip. Generally, the performance of electronic devices on the integrated circuit chip (e.g., transistors, resistors, capacitors, etc) is a major factor considered during scaling of those devices. Generally, a non-planar transistor architecture (e.g., FinFET, Trigate, Gate-All-Around (GAA)) refers to an architecture where the transistor channel is surrounded by one or more gates on multiple surfaces. Typically, a non-planar transistor has a fin grown on a silicon substrate. Many techniques have been developed to manufacture devices with non-Si channel materials, e.g., Ge, SiGe, and III-V materials. Significant process improvements, however, are still needed to integrate these materials onto Si wafers.
As the transistors scale down, the transistors increasingly suffer from the undesirable subfin leakage current that negatively impacts the device performance. One method to suppress the leakage current in a subfin layer of the non-planar device is to implant a dopant into the subfin layer to form a junction isolation. This method is not scalable and becomes harder to implement for current and future logic transistor technologies as the size of the devices decreases and the density of the devices increases. For example, in a germanium (Ge) p-type Metal Oxide Semiconductor (PMOS) device, the subfin layer is doped with a n-type dopant species (e.g., arsenic (As) and phosphorous (P)) to form a junction isolation. As the diffusion speed of the n-type dopant species in Ge is very fast it is very difficult to achieve an abrupt junction and it is impossible to contain the diffusion of the n-type species into the channel region.
Another solution to suppress the leakage current in the subfin layer of the Ge non-planar transistor is to use a silicon germanium (SiGe) as the subfin layer. Because of the lattice constant mismatch between Ge and SiGe, the Ge channel is strained and the channel thickness is limited to the critical thickness to which Ge can be grown on SiGe. This limits the fin thickness. For example, there can only be 20 nm or less of Ge on Si30Ge70 before the Ge film quality degrades due to formation of misfit dislocations. Additionally, a parallel conduction in SiGe prohibits scaling the channel length to the dimensions relevant to the current and future technology requirements.